CWE-1332: Improper Handling of Faults that Lead to Instruction Skips
The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.
How it's found
Improper Handling of Faults that Lead to Instruction Skips is typically found by tracing untrusted input from where it enters the system to the point where it is used without the check or neutralization this weakness describes, combining manual code review with dynamic testing.
The operating conditions of hardware may change in ways that cause unexpected behavior to occur, including the skipping of security-critical CPU instructions. Generally, this can occur due to electrical disturbances or when the device operates outside of its expected conditions. In practice, application code may contain conditional branches that are security-sensitive (e.g., accepting or rejecting a user-provided password). These conditional branches are typically implemented by a single conditional branch instruction in the program binary which, if skipped, may lead to effectively flipping the branch condition - i.e., causing the wrong security-sensitive branch to be taken. This affects processes such as firmware authentication, password verification, and other security-sensitive decision points. Attackers can use fault injection techniques to alter the operating conditions of hardware so that security-critical instructions are skipped more frequently or more reliably than they would in a "natural" setting.
Vulnerable vs. safe
The card emits the credentials when a voltage anomaly is injected into the power line to the device at a particular time after providing an incorrect PIN to the card, causing the internal program to accept the incorrect PIN.add an internal filter or internal power supply in series with the power supply pin on the device
add sensing circuitry to reset the device if out of tolerance conditions are detected
add additional execution sensing circuits to monitor the execution order for anomalies and abort the action or reset the device under fault conditionsConsequences
- Bypass Protection Mechanism, Alter Execution Logic, Unexpected State: Depending on the context, instruction skipping can have a broad range of consequences related to the generic bypassing of security critical code.
Mitigations
- Architecture and Design: Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.
- Architecture and Design: Design strategies for ensuring safe behavior if instructions attempt to be skipped.
- Architecture and Design: Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.
- Implementation: Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.
- Implementation: Use redundant operations or canaries to detect and respond to faults.
- Implementation: Ensure that fault mitigations are strong enough in practice. For example, a low power detection mechanism that takes 50 clock cycles to trigger at lower voltages may be an insufficient security mechanism if the instruction counter has already progressed with no other CPU activity occurring.
Where this fits in a TurboPentest engagement
This weakness is not covered by the automated black-box pentest. IntegSec pentesters cover it in a manual engagement.
Frequently asked questions
What is CWE-1332?
The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.
How do you find Improper Handling of Faults that Lead to Instruction Skips?
Improper Handling of Faults that Lead to Instruction Skips is typically found by tracing untrusted input from where it enters the system to the point where it is used without the check or neutralization this weakness describes, combining manual code review with dynamic testing.
What is the impact of CWE-1332?
Bypass Protection Mechanism, Alter Execution Logic, Unexpected State: Depending on the context, instruction skipping can have a broad range of consequences related to the generic bypassing of security critical code.
Does TurboPentest test for Improper Handling of Faults that Lead to Instruction Skips?
This weakness is not covered by the automated black-box pentest. IntegSec pentesters cover it in a manual engagement.
Related CWEs
Written and reviewed by
Michel Chamberland - Founder & CEO, IntegSec
CISSP, OSCP, OSCE, CEH, GIAC, CCSK · 20+ years in offensive security
Michel has spent 20+ years on offensive security teams including IBM X-Force Red and Trustwave SpiderLabs, leading penetration tests, red team engagements, and breach response for Fortune 500 customers. He is the founder of IntegSec and the architect of TurboPentest.
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