CWE-1239: Improper Zeroization of Hardware Register

How it's found

Improper Zeroization of Hardware Register is a specific, narrowly defined instance of a broader pattern. Testers confirm it with targeted code review and a proof-of-concept input that exercises the exact code path this weakness describes.

Hardware logic operates on data stored in registers local to the hardware block. Most hardware IPs, including cryptographic accelerators, rely on registers to buffer I/O, store intermediate values, and interface with software. The result of this is that sensitive information, such as passwords or encryption keys, can exist in locations not transparent to the user of the hardware logic. When a different entity obtains access to the IP due to a change in operating mode or conditions, the new entity can extract information belonging to the previous user if no mechanisms are in place to clear register contents. It is important to clear information stored in the hardware if a physical attack on the product is detected, or if the user of the hardware block changes. The process of clearing register contents in a hardware IP is referred to as zeroization in standards for cryptographic hardware modules such as FIPS-140-2 [REF-267].

Vulnerable vs. safe

startHash <= 0;newMessage <= 0;data[0] <= 0;data[1] <= 0;data[2] <= 0;...data[14] <= 0;data[15] <= 0;beginif(~(rst_ni && ~rst_3))begin// Implement SHA256 I/O memory map interface// Write sidealways @(posedge clk_i)......

startHash <= 0;newMessage <= 0;data[0] <= 0;data[1] <= 0;data[2] <= 0;...data[14] <= 0;data[15] <= 0;beginend

begindata[0] <= 0;

data[1] <= 0;

data[2] <= 0;

...

data[14] <= 0;

data[15] <= 0;

endelse if(hashValid && ~hashValid_r)if(~(rst_ni && ~rst_3))begin// Implement SHA256 I/O memory map interface// Write sidealways @(posedge clk_i)......

Consequences

• Varies by Context: The consequences will depend on the information disclosed due to the vulnerability.

Mitigations

• Architecture and Design: Every register potentially containing sensitive information must have a policy specifying how and when information is cleared, in addition to clarifying if it is the responsibility of the hardware logic or IP user to initiate the zeroization procedure at the appropriate time.

Where this fits in a TurboPentest engagement

This weakness is not covered by the automated black-box pentest. IntegSec pentesters cover it in a manual engagement.

Frequently asked questions

Related CWEs

• Base weakness
  CWE-226: Sensitive Information in Resource Not Removed Before Reuse