CWE-1223: Race Condition for Write-Once Attributes
A write-once register in hardware design is programmable by an untrusted software component earlier than the trusted software component, resulting in a race condition issue.
How it's found
Race Condition for Write-Once Attributes is typically found by tracing untrusted input from where it enters the system to the point where it is used without the check or neutralization this weakness describes, combining manual code review with dynamic testing.
Integrated circuits and hardware IP software programmable controls and settings are commonly stored in register circuits. These register contents have to be initialized at hardware reset to defined default values that are hard coded in the hardware description language (HDL) code of the hardware unit. A common security protection method used to protect register settings from modification by software is to make them write-once. This means the hardware implementation only allows writing to such registers once, and they become read-only after having been written once by software. This is useful to allow initial boot software to configure systems settings to secure values while blocking runtime software from modifying such hardware settings. Implementation issues in hardware design of such controls can expose such registers to a race condition security flaw. For example, consider a hardware design that has two different software/firmware modules executing in parallel. One module is trusted (module A) and another is untrusted (module B). In this design it could be possible for Module B to send write cycles to the write-once register before Module A. Since the field is write-once the programmed value from Module A will be ignored and the pre-empted value programmed by Module B will be used by hardware.
Vulnerable vs. safe
input [15:0] Data_in,input Clk,input ip_resetn,input global_resetn,input write,output reg [15:0] Data_out
Data_out <= 16'h0000;Write_once_status <= 1'b0;beginend
Data_out <= Data_in & 16'hFFFE; // Input data written to register after masking bit 0Write_once_status <= 1'b1; // Write once status set after first write.beginend
Data_out[15:1] <= Data_out[15:1];Data_out[0] <= Write_once_status;beginendmodule register_write_once_example();reg Write_once_status;always @(posedge Clk or negedge ip_resetn)if (~ip_resetn)else if (write & ~Write_once_status)else if (~write)endmoduleMust confirm the Write_once_status (bit 0) value is zero, before programming register. If another agent has programmed the register before, then Write_once_status value will be one.
After writing to the register, the trusted software can issue a read to confirm that the valid setting has been programmed.Trusted firmware or software trying to set the write-once field:Consequences
- Bypass Protection Mechanism: System configuration cannot be programmed in a secure way.
Mitigations
- Architecture and Design: During hardware design, all register write-once or sticky fields must be evaluated for proper configuration.
Where this fits in a TurboPentest engagement
This weakness is not covered by the automated black-box pentest. IntegSec pentesters cover it in a manual engagement.
Frequently asked questions
What is CWE-1223?
A write-once register in hardware design is programmable by an untrusted software component earlier than the trusted software component, resulting in a race condition issue.
How do you find Race Condition for Write-Once Attributes?
Race Condition for Write-Once Attributes is typically found by tracing untrusted input from where it enters the system to the point where it is used without the check or neutralization this weakness describes, combining manual code review with dynamic testing.
What is the impact of CWE-1223?
Bypass Protection Mechanism: System configuration cannot be programmed in a secure way.
Does TurboPentest test for Race Condition for Write-Once Attributes?
This weakness is not covered by the automated black-box pentest. IntegSec pentesters cover it in a manual engagement.
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Written and reviewed by
Michel Chamberland - Founder & CEO, IntegSec
CISSP, OSCP, OSCE, CEH, GIAC, CCSK · 20+ years in offensive security
Michel has spent 20+ years on offensive security teams including IBM X-Force Red and Trustwave SpiderLabs, leading penetration tests, red team engagements, and breach response for Fortune 500 customers. He is the founder of IntegSec and the architect of TurboPentest.
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